Power-gating is a technique to save power in digital circuits. It consists of cutting off the supply voltage to most of the digital components of an integrated circuit (IC) during periods of hardware low utilization (e.g., sleep periods). Thus, in an IC with power-gating, there are two different supply nets: a VDD, which is always powered up; and a virtual VDD (hereinafter ‘VDD_virtual’), which is powered down on some operation modes. VDD is connected to virtual VDD through a switch network.
During the sleep period the state of the IC is preserved by keeping some memories powered up. When the whole IC is to re-start operation, the virtual VDD has to be re-connected to VDD (typically 1.8V) to establish regular power supply voltage. If the wake-up process is not controlled, excessive transient currents can cause the VDD voltage to drop substantially—potentially corrupting the chip state—and damage the IC metal leads or transistors. Further, excessive transient currents may cause excessive noise, and the excessive noise coupling can also corrupt memories.
Various approaches to power-gating have been developed. In one approach, the switch network consists of many small switches and the transient current is controlled by turning on the small switches in delayed groups. Thus, at any given time, only a portion of the many switches are turned on and the transient current is reduced. FIG. 1 shows a typical switch network that comprises a plurality of switches SW1 to SWn, and digital circuits powered by the virtual VDD. The number of small switches can be as high as thousands in common integrated circuits. And as shown in FIG. 1, the switches are mixed with the regular digital circuitry.
In the prior art power-gating techniques such as FIG. 1, these switches need to be placed during a process called “digital implementation” when the digital design is translated from a high-level language, like Verilog, to actual digital gates. These switches make digital implementation much harder because it is hard to know in advance how many switches will be needed or how to distribute them across the circuit. Further, each switch or switch group must be able to cope with the local worst case of current consumption, and each switch has to support the whole VDD across their drain-to-source voltage, which has a severe reliability problem.
The reliability problem cannot be solved by using larger voltage devices because of the extra layout area required for the wells. One approach towards this problem is illustrated by FIG. 2. As shown in FIG. 2, during normal operations, switches 204.1 and 204.2 connect internal power supplies PGVDD and PGVSS to external power supplies VDD and VSS to provide power to a power-controlled circuit 202. During the standby mode, the internal power supplies PGVDD and PGVSS are connected by switches 204.3 and 204.4 to a voltage at the middle between the VDD and VSS power supplies. Accordingly, in standby operations, the voltage across the gate oxides of switches 204.1 and 204.2 is prevented from exceeding (VDD−VSS)/2 and breakdown is prevented. However, this method has a severe penalty in area, in-rush (voltage) drop and complexity.
Many switches spread out in the digital circuit also make it impossible to eliminate the presence of the switches using a Focused ion beam (FIB) or a simple metal edit. Further, because the switches are mixed with the regular logic, a full-width VDD lead is needed to carry the whole current from the cell outside to the switch and a wide track is also required for the VDD_virtual. This results in an area penalty compared to a regular circuit without power-gating. Moreover, digital implementation requires more iterations and often there is no digital flow or tools to help with this process. In addition, it is difficult to know when the digital circuit is finally ready for operation and the wake-up process completed. Also, in order to calculate the position and number of switches there is information that is needed from the digital circuitry. However, for some IP blocks this information might not be available.
Therefore, although power-gating is a technique able to deliver significant power savings, adding a complex switch network to implement the power-gating in the current technology is costly in terms of time and design resources. Accordingly, there is a need in the art for providing a power-gating switch circuit outside the digital circuitry.